Semiconductor device comprising a mosfet having a resurf region and higher peak impurity concentration diffusion region in the resurf region

ABSTRACT

Provided is a semiconductor device including: an N-type diffusion layer being a second region, formed in a surface portion of a P-type diffusion layer being a first region, to function as a RESURF region; an N-type buried diffusion layer being a third region formed in a bottom portion of the second region, close to a high-side circuit; and a MOSFET using the second region as a drift layer. The MOSFET includes a thermal oxide film formed between an N-type diffusion layer being a fourth region serving as a drain region and an N-type diffusion layer being a sixth region serving as a source region, and an N-type diffusion layer being a seventh region formed below the thermal oxide film. The seventh region has an end portion close to a low-side circuit, being closer to the low-side circuit than an end portion of the third region close to the low-side circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. patent application Ser. No.17/075,032 filed Oct. 20, 2020, which claims benefit of priority toJapanese Patent Application No. 2019-234187 filed Dec. 25, 2019, theentire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION Field of the Invention

The present disclosure relates to a semiconductor device including ametal oxide semiconductor field effect transistor (MOSFET).

Description of the Background Art

An integrated circuit (IC) for power control, which is mainly used fordriving a gate of a semiconductor device for electric power, typicallyincludes a low-side circuit that operates using a ground (GND) potentialas a reference potential, and a high-side circuit that operates using,for example, a potential such as a floating potential, different fromthe GND potential as a reference potential, and a level shift circuitthat transmits a signal between the low-side circuit and the high-sidecircuit.

There is known a technique in which a low-side circuit region and ahigh-side circuit region are separated by a reduced surface field(RESURF) region to form a MOSFET constituting a level shift circuit inthe RESURF region (e.g., refer to JP 3917211 B2). This MOSFET needs tomaintain breakdown voltage equivalent to that of the RESURF region.There is also known a condition of the RESURF region, in which a valueof the product of a vertical depth (thickness) t [cm] and an impurityconcentration N[cm⁻³] of the RESURF region is limited to enable theRESURF region to maintain high breakdown voltage by being completelydepleted when breakdown voltage is maintained (e.g., refer to U.S. Pat.No. 4,292,642 and Philips Journal of Research Vol. 35 No. 1 1980).According to Philips Journal of Research, a condition, N×t<6.9×10¹¹ cm⁻²(hereinafter, this condition is referred to as a “RESURF condition”)needs to be satisfied.

Although an IC including a low-side circuit and a high-side circuitrequires a power supply for driving each of the low-side circuit and thehigh-side circuit, there is known a system in which a bootstrap circuitis provided in the IC as a power supply for the high-side circuit. Thereis also known a technique using a MOSFET formed in a RESURF region, as ahigh breakdown voltage element in this bootstrap circuit (e.g., refer toJP 5488256 B2).

As described above, the semiconductor device including the RESURF regionneeds to maintain high breakdown voltage by completely depleting theRESURF region when breakdown voltage is maintained, so that an impurityconcentration of the RESURF region is limited. This hinders reduction inon-resistance of the MOSFET formed in the RESURF region. Increasing alength of the RESURF region formed with the MOSFET enables improvingbreakdown voltage performance of the MOSFET, but accordingly theon-resistance of the MOSFET increases. That is, the MOSFET formed in theRESURF region has a trade-off relationship between the improvement ofbreakdown voltage performance and the reduction in on-resistance.

SUMMARY

The present disclosure is made to solve the above problems, and anobject thereof is to improve the trade-off between the improvement ofbreakdown voltage performance and the reduction in on-resistance of theMOSFET formed in the RESURF region.

A semiconductor device according to the present disclosure includes: asemiconductor substrate formed with a first region of a firstconductivity type; a second region that is a RESURF region of a secondconductivity type formed in a surface portion of the first region toseparate a high-side circuit and a low-side circuit from each other; athird region of the second conductivity type formed at least in a bottomportion of the second region close to the high-side circuit, having ahigher peak concentration of impurities than the second region; and aMOSFET using the second region as a drift layer. The MOSFET includes: afourth region serving as a drain region of the second conductivity typeformed in the surface portion of the second region, having a higher peakconcentration of impurities than the second region; a sixth regionserving as a source region of the second conductivity type formed in asurface portion of a fifth region of the first conductivity type or in asurface portion of the first region, in a region closer to the low-sidecircuit than the fourth region, the fifth region being provided in thesecond region; a first thermal oxide film formed on a surface of thesecond region, in a region between the fourth region and the sixthregion; and a seventh region of the second conductivity type formed in asurface portion of the second region below the first thermal oxide film,having a higher peak concentration of impurities than the second region.An end portion of the seventh region close to the low-side circuit islocated closer to the low-side circuit than an end portion of the thirdregion close to the low-side circuit.

The semiconductor device according to the present disclosure allowson-resistance of the MOSFET to be reduced by the seventh region, andimproves the breakdown voltage performance by dispersing a locationwhere an electric field is concentrated into the third region and theseventh region. This enables improving the trade-off between theimprovement of breakdown voltage performance of the MOSFET formed in theRESURF region and the reduction in on-resistance.

These and other objects, features, aspects and advantages of the presentdisclosure will become more apparent from the following detaileddescription of the present disclosure when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of a MOSFET formed in a RESURF region of asemiconductor device according to a first preferred embodiment;

FIG. 2 is a sectional view illustrating structure of a conventionalMOSFET;

FIG. 3 is a diagram illustrating structure in which a third region(N-type buried diffusion layer 2) is added to a conventional MOSFET;

FIG. 4 is a diagram illustrating structure in which a seventh region(N-type diffusion layer 14) is added to a conventional MOSFET;

FIG. 5 is a diagram showing results of simulating horizontal potentialdistribution near a surface of a semiconductor substrate for the MOSFETof the first preferred embodiment and the conventional MOSFET whenbreakdown voltage is maintained;

FIG. 6 is a diagram showing results of simulating horizontal electricfield distribution near a surface of a semiconductor substrate for theMOSFET of the first preferred embodiment and the conventional MOSFETwhen breakdown voltage is maintained;

FIG. 7 is a diagram showing results of simulating horizontal electricfield distribution in a portion at a depth at which the electric fieldis to be maximum near the third region (N-type buried diffusion layer 2)of the MOSFET of the first preferred embodiment, for the MOSFET of thefirst preferred embodiment and the conventional MOSFET;

FIG. 8 is a diagram showing results of simulating a relationship betweena lateral length of a seventh region (N-type diffusion layer 14) andbreakdown voltage performance for the MOSFET of the first preferredembodiment and the MOSFET of FIG. 4 ;

FIG. 9 is a diagram showing measurement results of a current value andbreakdown voltage during an ON operation for the MOSFET of the firstpreferred embodiment and the conventional MOSFET;

FIG. 10 is a sectional view of a MOSFET formed in a RESURF region of asemiconductor device according to a second preferred embodiment;

FIGS. 11 and 12 are each a diagram illustrating an example of structureof an N-type diffusion layer 15;

FIG. 13 is a sectional view of a MOSFET formed in a RESURF region of asemiconductor device according to a third preferred embodiment;

FIG. 14 is a diagram showing results of simulating impurityconcentration distribution in a depth direction of the seventh region(N-type diffusion layer 14);

FIG. 15 is a sectional view of a MOSFET formed in a RESURF region of asemiconductor device according to a fourth preferred embodiment;

FIG. 16 is a diagram showing results of simulating a relationshipbetween a length of a first polysilicon layer (polysilicon layer 10)extending toward a low-side circuit and breakdown voltage of a MOSFET;

FIG. 17 is a sectional view of a MOSFET formed in a RESURF region of asemiconductor device according to a fifth preferred embodiment;

FIG. 18 is a diagram illustrating an example of a high-side circuit;

FIG. 19 is a plan view illustrating a semiconductor device and asurrounding high-side circuit region of a sixth preferred embodiment;

FIG. 20 is a plan view illustrating the semiconductor device, thesurrounding high-side circuit region, and a lateral high breakdownvoltage MOSFET of the sixth preferred embodiment;

FIG. 21 is a diagram illustrating a configuration of a drive ICaccording to a seventh preferred embodiment;

FIG. 22 is a diagram illustrating a configuration of a level shiftcircuit;

FIG. 23 is a diagram illustrating a modification of the drive ICaccording to the seventh preferred embodiment;

FIG. 24 is a diagram illustrating a configuration of a drive ICaccording to an eighth preferred embodiment; and

FIG. 25 is a sectional view of a MOSFET formed in a RESURF region of asemiconductor device according to a ninth preferred embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Preferred Embodiment

FIG. 1 is a sectional view of a lateral high breakdown voltage N-channelMOSFET formed in a RESURF region of a semiconductor device according toa first preferred embodiment. Hereinafter, unless otherwise specified, a“MOSFET” refers to a lateral MOSFET formed in a RESURF region. Then, theleft side direction in FIG. 1 is defined as the inside of thesemiconductor device, and the right side direction is defined as theoutside of the semiconductor device. In the following description, afirst conductivity type is a P-type and a second conductivity type is anN-type. However, conversely, the first conductivity type may be the Ntype and the second conductivity type may be the P type.

The semiconductor device according to the first preferred embodiment isformed using a semiconductor substrate 100 of the P-type, formed with aP-type diffusion layer 1 as a first region. The semiconductor substrate100 is formed with respective regions described below, and in thefollowing description, a P-type region of the semiconductor substrate100 that remains other than these formed regions is referred to as the“P-type diffusion layer 1”. Here, although the semiconductor substrate100 is made of silicon (Si), a wide band gap semiconductor made ofsilicon carbide (SiC), gallium nitride (GaN), or the like may be used. Asemiconductor device using the wide band gap semiconductor is superiorin operation at high voltage, large current, and high temperature to aconventional semiconductor device using silicon.

The semiconductor substrate 100 includes a surface portion formed withan N-type diffusion layer 3 as a second region. Although not illustratedin FIG. 1 , a high-side circuit is formed inside the N-type diffusionlayer 3, and a low-side circuit is formed outside the N-type diffusionlayer 3. Then, the N-type diffusion layer 3 functions as a RESURF regionthat separates the high-side circuit and the low-side circuit from eachother. That is, when the N-type diffusion layer 3 has an impurityconcentration indicated as N [cm⁻³] and a depth indicated as t [cm], thecondition, N×t<6.9×10¹¹ cm⁻², i.e., the RESURF condition, is satisfied.

The N-type diffusion layer 3 is provided in at least its inner bottomportion (close to the high-side circuit) with an N-type buried diffusionlayer 2 having a higher peak concentration of impurities than that ofthe N-type diffusion layer 3, as a third region. The N-type burieddiffusion layer 2 achieves not only an effect of suppressing verticalparasitic operation of elements in the high-side circuit, but also aneffect of preventing operation of the elements in the high-side circuitfrom being adversely affected by allowing a depletion layer in theN-type diffusion layer 3 to extend into the high-side circuit when thebreakdown voltage is maintained.

The semiconductor device according to the first preferred embodimentincludes a lateral high breakdown voltage N-channel MOSFET having theN-type diffusion layer 3 as a drift layer. Structure of the MOSFET willbe described below.

The N-type diffusion layer 3 includes a surface portion formed with anN-type diffusion layer 4 as a fourth region and a P-type diffusion layer6 as a fifth region. The N-type diffusion layer 4 has a higher peakconcentration of impurities than the N-type diffusion layer 3 and servesas a drain region of the MOSFET. The P-type diffusion layer 6 includes asurface portion formed with an N-type diffusion layer 7 as a sixthregion and a P-type diffusion layer 8 having a higher peak concentrationof impurities than the P-type diffusion layer 6. The N-type diffusionlayer 7 serves as a source region of the MOSFET. The P-type diffusionlayer 6 serves as a back gate of the MOSFET, and the P-type diffusionlayer 8 serves as a contact region for electrically connecting theP-type diffusion layer 6 and a back gate electrode 24 described later.

The N-type diffusion layer 3 has a surface between the N-type diffusionlayer 4 and the P-type diffusion layer 6 (i.e., between the N-typediffusion layer 4 and the N-type diffusion layer 7), and a surfaceinside of the N-type diffusion layer 4, the surfaces each being formedwith a thermal oxide film 9. The thermal oxide film 9 between the N-typediffusion layer 4 and the P-type diffusion layer 6 serves as a firstthermal oxide film, and the thermal oxide film 9 inside the N-typediffusion layer 4 serves as a second thermal oxide film.

The N-type diffusion layer 3 includes a surface portion below thethermal oxide film 9 between the N-type diffusion layer 4 and the P-typediffusion layer 6, the surface portion being formed with an N-typediffusion layer 14 having a higher peak concentration of impurities thanthe N-type diffusion layer 3, as a seventh region. The N-type diffusionlayer 14 does not satisfy the RESURF condition. That is, when the N-typediffusion layer 14 has an impurity concentration indicated as N [cm⁻³]and a depth indicated as t [cm], a relationship, N×t>6.9×10¹¹ cm⁻², issatisfied. The N-type diffusion layer 14 has an outer end portion,located closer to the low-side circuit than an outer end portion of theN-type buried diffusion layer 2. That is, the N-type diffusion layer 14extends outward of the N-type buried diffusion layer 2. Although theN-type diffusion layer 14 may be in contact with the N-type burieddiffusion layer 2, the N-type diffusion layer 14 is here housed in theN-type diffusion layer 3, and the N-type diffusion layer 14 and theN-type buried diffusion layer 2 are separated from each other. Althoughthe N-type diffusion layer 14 is formed overlapping the N-type diffusionlayer 4 in FIG. 1 , the layers may not overlap each other.

Below the thermal oxide film 9 inside the N-type diffusion layer 4, anN-type diffusion layer 5 is formed as an eighth region to prevent fieldinversion. This N-type diffusion layer 5 may be eliminated.

The thermal oxide film 9 between the N-type diffusion layer 4 and theP-type diffusion layer 6 has an inner end portion covered with apolysilicon layer 10 as a first polysilicon layer. The thermal oxidefilm 9 has an outer end portion covered with a polysilicon layer 11 as asecond polysilicon layer. The polysilicon layer 11 extends from the endportion on the outside of the thermal oxide film 9 between the N-typediffusion layer 4 and the P-type diffusion layer 6 to above the N-typediffusion layer 7 to cover surfaces of the N-type diffusion layer 3 andthe P-type diffusion layer 6 in a region between the thermal oxide film9 and the N-type diffusion layer 7.

The semiconductor substrate 100 has a surface formed with an insulatingfilm 12. On the insulating film 12, a reference potential electrode 20for fixing a potential of the P-type diffusion layer 1 to a referencepotential, and a gate electrode 21, a source electrode 23, a drainelectrode 22, and a back gate electrode 24 of the MOSFET, are eachformed partially embedded in the insulating film 12. The referencepotential electrode 20 is connected to the P-type diffusion layer 1. Thegate electrode 21 is provided on the polysilicon layer 11 and faces asurface of the P-type diffusion layer 8 in a region between the N-typediffusion layer 7 and the N-type diffusion layer 3. During an ONoperation of the MOSFET, a channel is formed in the P-type diffusionlayer 8 below the gate electrode 21. The source electrode 23 isconnected to the N-type diffusion layer 7 serving as the source regionof the MOSFET. The drain electrode 22 is connected to the N-typediffusion layer 4 serving as the drain region of the MOSFET, and partlyreaches an upper surface of the polysilicon layer 10. The back gateelectrode 24 is connected to the P-type diffusion layer 8, and iselectrically connected to the P-type diffusion layer 6 serving as a backgate through the P-type diffusion layer 8.

The semiconductor device according to the first preferred embodiment hascharacteristics in which the N-type buried diffusion layer 2 and theN-type diffusion layer 14 are provided, and the N-type diffusion layer14 has the outer end portion (close to the low side circuit), locatedcloser to the low-side circuit than the outer end portion of the N-typeburied diffusion layer 2. Hereinafter, effects obtained by thecharacteristics will be described below.

The conventional semiconductor device has a structure without the N-typeburied diffusion layer 2 and the N-type diffusion layer 14, asillustrated in FIG. 2 . The semiconductor device of FIG. 2 is configuredsuch that a depletion layer extends from a PN junction between theN-type diffusion layer 3 and the P-type diffusion layer 1 when thebreakdown voltage is maintained with the drain electrode 22 to be at ahigh potential. At this time, the N-type diffusion layer 3 is completelydepleted by a RESURF effect, thereby achieving high breakdown voltage ofthe MOSFET.

For example, when the semiconductor device of FIG. 2 is provided withthe N-type buried diffusion layer 2 being the third region asillustrated in FIG. 3 , the semiconductor device can obtain not only aneffect of suppressing vertical parasitic operation of elements in thehigh-side circuit, but also an effect of preventing operation of theelements in the high-side circuit from being adversely affected by adepletion layer when the breakdown voltage is maintained, as describedabove. However, when the breakdown voltage is maintained, the N-typeburied diffusion layer 2 is not completely depleted. Thus, an electricfield is concentrated in the N-type buried diffusion layer 2, so thatbreakdown voltage performance of the MOSFET deteriorates.

For example, when the semiconductor device of FIG. 2 is provided withthe N-type diffusion layer 14 being the seventh region as illustrated inFIG. 4 , increasing the N-type diffusion layer 14 in depth in a verticaldirection (a direction perpendicular to a surface of the N-typediffusion layer 3) and in length in a lateral direction (a directionfrom the high-side circuit toward the low-side direction) enablesreducing on-resistance of the MOSFET. However, when the breakdownvoltage is maintained, an electric field concentrates on the end portionof the N-type diffusion layer 14. Thus, the breakdown voltageperformance deteriorates as the N-type diffusion layer is increased indepth and length. That is, there is a trade-off relationship between theeffect of reducing the on-resistance of the MOSFET using the N-typediffusion layer 14 and the breakdown voltage performance of the MOSFET.

In contrast, the semiconductor device according to the first preferredembodiment is configured such that both of the N-type buried diffusionlayer 2 and the N-type diffusion layer 14 are formed in the N-typediffusion layer 3. In this case, the N-type diffusion layer 14 reducesthe on-resistance of the MOSFET, and electric field concentration occursin both the N-type buried diffusion layer 2 and the N-type diffusionlayer 14. Thus, locations where the electric field concentration occursare dispersed to improve the breakdown voltage performance of theMOSFET. As a result, the trade-off between the breakdown voltageperformance and the on-resistance is improved as compared with thesemiconductor devices of FIGS. 2 to 4 .

However, when the N-type diffusion layer 14 has a short length, theelectric field is not remarkably concentrated in the N-type diffusionlayer 14. Thus, the electric field is not dispersed into the N-typeburied diffusion layer 2 and the N-type diffusion layer 14 to increasestrength of the electric field generated in the N-type buried diffusionlayer 2, so that the above effect cannot be sufficiently obtained. Forthis reason, the semiconductor device of the first preferred embodimentis configured such that the N-type diffusion layer 14 is increased inlength to allow the outer end portion of the N-type diffusion layer 14to be located outside the outer end portion of the N-type burieddiffusion layer 2, thereby allowing the electric field to be alsoconcentrated in the N-type diffusion layer 14. The breakdown voltageperformance is most improved in the first embodiment under conditionswhere the N-type buried diffusion layer 2 has a maximum electric fieldstrength equal to a maximum electric field strength in the N-typediffusion layer 14 when the breakdown voltage is maintained.

FIG. 5 shows results of simulating horizontal potential distributionnear a surface of the semiconductor substrate 100 for the MOSFET of thefirst preferred embodiment and the conventional MOSFET when thebreakdown voltage is maintained. FIG. 5 includes the solid line graphshowing the potential distribution of the MOSFET of the firstembodiment, and the broken line graph showing the potential distributionof the conventional MOSFET. The solid line graph shows a flat region inits left end portion that corresponds to the N-type diffusion layer 14.As shown in FIG. 5 , the MOSFET of the first preferred embodimentincludes the N-type diffusion layer 14 with a high impurityconcentration, so that the N-type diffusion layer 14 has a higherpotential than that of the conventional MOSFET. From this, it turns outthat the MOSFET of the first preferred embodiment has the electric fieldthat is concentrated not only in the N-type buried diffusion layer 2 butalso in the N-type diffusion layer 14 when the breakdown voltage ismaintained.

FIG. 6 shows results of simulating horizontal electric fielddistribution near the surface of the semiconductor substrate 100 for theMOSFET of the first preferred embodiment and the conventional MOSFETwhen the breakdown voltage is maintained. FIG. 7 shows results ofsimulating horizontal electric field distribution in a portion at adepth at which the electric field is to be maximum near the N-typeburied diffusion layer 2 of the MOSFET of the first preferredembodiment, for the MOSFET of the first preferred embodiment and theconventional MOSFET. FIGS. 6 and 7 each includes the solid line graphshowing electric field distribution of the MOSFET of the first preferredembodiment, and the broken line graph showing the electric fielddistribution of the conventional MOSFET. The respective simulations ofFIGS. 5 to 7 are all identical in bias potential that is set whenbreakdown voltage is maintained.

FIG. 6 shows the graph of the MOSFET of the first preferred embodimentin which a peak of the electric field strength appears in a portion thatcorresponds to the outer end portion of the N-type diffusion layer 14.When the electric field is concentrated in the outer end portion of theN-type diffusion layer 14 as described above, the MOSFET of the firstpreferred embodiment has a lower maximum value of the electric fieldthan the conventional MOSFET as shown in FIG. 7 . This enables theMOSFET of the first preferred embodiment to have higher breakdownvoltage performance than the conventional MOSFET.

FIG. 8 shows results of simulating a relationship between a laterallength of the N-type diffusion layer 14 and breakdown voltageperformance for the MOSFET of the first preferred embodiment and theconventional MOSFET including the N-type diffusion layer 14 (FIG. 4 ).FIG. 8 includes the solid line graph showing breakdown voltagecharacteristics of the MOSFET of the first preferred embodiment, and thebroken line graph showing breakdown voltage characteristics of theMOSFET of FIG. 4 . The MOSFET of the first preferred embodimentincluding both the N-type buried diffusion layer 2 and the N-typediffusion layer 14 has an improved trade-off between breakdown voltageperformance and on-resistance as compared with the MOSFET of FIG. 4including only the N-type diffusion layer 14.

FIG. 9 is a diagram showing measurement results of a current value andbreakdown voltage during an ON operation for the MOSFET of the firstpreferred embodiment and the conventional MOSFET. FIG. 9 shows a blackdot that is a measurement result of the MOSFET of the first embodiment,and a white dot that is a measurement result of the conventional MOSFET.FIG. 9 shows a graph with a vertical axis and a horizontal axis that arenormalized by measured values of the conventional MOSFET. The MOSFET ofthe first embodiment is improved in breakdown voltage performance andreduced in on-resistance as compared with the conventional MOSFET, sothat a tendency as in the above simulation results is found.

As described above, the semiconductor device according to the firstpreferred embodiment enables improving the trade-off between thereduction in the on-resistance and the improvement of the breakdownvoltage performance in the MOSFET including the N-type diffusion layer 3serving as a drift layer by providing both the N-type buried diffusionlayer 2 (second region) having a higher impurity peak concentration thanthe RESURF region, and the N-type diffusion layer 14 (seventh region),in the N-type diffusion layer 3 serving as the RESURF region.

Second Preferred Embodiment

FIG. 10 is a sectional view of a MOSFET formed in a RESURF region of asemiconductor device according to a second preferred embodiment. FIG. 10is different from FIG. 1 in structure in which an N-type diffusion layer15 having a peak concentration of impurities that is lower than that ofan N-type diffusion layer 14 and higher than that of an N-type diffusionlayer 3 is provided as a ninth region outside (close to the low-sidecircuit) the N-type diffusion layer 14 being the seventh region.

When the MOSFET of the second preferred embodiment includes the N-typediffusion layer 15, an impurity concentration of a drift layer partiallyincreases to higher than that of the MOSFET of the first preferredembodiment. Thus, the MOSFET of the second preferred embodiment has alower on-resistance than that of the first preferred embodiment.

The N-type diffusion layer 15 has a lower impurity concentration thanthe N-type diffusion layer 14, and thus is liable to be depleted. Thus,disposing the N-type diffusion layer 15 enables suppressingconcentration of an electric field when breakdown voltage is maintained.This enables breakdown voltage performance to be improved as comparedwith the first preferred embodiment.

As described above, the second preferred embodiment enables more effectsof reducing the on-resistance of the MOSFET and improving the breakdownvoltage performance to be obtained as compared with the firstembodiment. Thus, a trade-off between the reduction in the on-resistanceand the improvement of the breakdown voltage performance in the MOSFETcan be further improved as compared with the first preferred embodiment.

The N-type diffusion layer 15 may have an uneven distribution of theimpurity concentration, and thus may have an outer end portion with aconcentration lower than that in an inner portion, for example. In thatcase, the N-type diffusion layer 15 may be formed overlapping the N-typediffusion layer 14, and the N-type diffusion layer 15 may be formedoverlapping the entire N-type diffusion layer 14, for example. In otherwords, the N-type diffusion layer 14 may have a distribution of theimpurity concentration in which the outer end portion has a lowerconcentration than the inner portion.

Although the N-type diffusion layer 15 is one integrated region in FIG.10 , the N-type diffusion layer 15 may be composed of a plurality ofdiscretely formed regions. For example, the N-type diffusion layer 15may be composed of a plurality of line-shaped regions as in aperspective view of FIG. 11 , or the N-type diffusion layer 15 may becomposed of a plurality of dot-shaped regions as in a perspective viewof FIG. 12 . In this case, each of the plurality of regions constitutingthe N-type diffusion layer 15 has an impurity concentration that can beadjusted using a pattern shape including size or an interval of lines ordots (see FIG. 14 described later). Thus, when the N-type diffusionlayer 15 is composed of a plurality of discrete regions, the N-typediffusion layer 14 and the N-type diffusion layer 15 can be collectivelyformed in the same impurity implantation step. In that case, each of theplurality of regions constituting the N-type diffusion layer 15 has animpurity concentration equal to or lower than that of the N-typediffusion layer 14.

Third Preferred Embodiment

FIG. 13 is a sectional view of a MOSFET formed in a RESURF region of asemiconductor device according to a third preferred embodiment. Thethird preferred embodiment includes an N-type diffusion layer 14 being aseventh region provided below the thermal oxide film 9 in a regionbetween an N-type diffusion layer 4 and a P-type diffusion layer 6, andan N-type diffusion layer 5 being an eighth region provided below thethermal oxide film 9 inside the N-type diffusion layer 4, the layersbeing formed in the same impurity implantation step. Although FIG. 13illustrates the N-type diffusion layer 14 and the N-type diffusion layer5 that are connected, the layers may be separated from each other.

The present embodiment allows the N-type diffusion layer 14 and theN-type diffusion layer 5 to be formed in the same impurity implantationstep, so that the N-type diffusion layer 5 has an impurity concentrationthat is basically equal to an impurity concentration of the N-typediffusion layer 14. However, the N-type diffusion layer 14 and theN-type diffusion layer 5 may be different from each other in impurityconcentration by forming the N-type diffusion layer 14 or the N-typediffusion layer 5 from a plurality of discrete regions as with theN-type diffusion layer 15 of the second preferred embodiment. When theN-type diffusion layer 5 has an impurity concentration indicated as N1and the N-type diffusion layer 14 has an impurity concentrationindicated as N2, a relationship, 0.1×N1<N2<2×N1, is preferablysatisfied.

FIG. 14 shows results of simulating impurity concentration distributionin a depth direction of the N-type diffusion layer 14. FIG. 14 includesthe solid line graph showing distribution when an implantation mask witha sufficiently large opening is used in the impurity implantation stepof forming the N-type diffusion layer 14, and the broken line graphshowing distribution when the implantation mask has an opening in a sizeof 0.5 μm. FIG. 14 shows the graph with a horizontal axis representing avertical distance from a surface of the thermal oxide film 9, and avertical axis representing a relative value (value normalized by a peakvalue of the solid line graph) of an impurity concentration of theN-type diffusion layer 14. When the opening of the implantation mask hasa size of 0.5 μm, the impurity concentration can be reduced to about ⅕of a size of the opening of the implantation mask that is sufficientlylarge. As described above, the impurity concentrations of the N-typediffusion layer 14 and the N-type diffusion layer 5 can be controlled byadjusting the size of the opening of the implantation mask, i.e., thesize of the impurity implantation region.

As in the third preferred embodiment, the N-type diffusion layer 14 andthe N-type diffusion layer 5 can be formed in the same impurityimplantation step. This enables reduction in the number of impurityimplantation steps, so that a manufacturing step of the semiconductordevice can be simplified. The third preferred embodiment may be combinedwith the second preferred embodiment.

Fourth Preferred Embodiment

FIG. 15 is a sectional view of a MOSFET formed in a RESURF region of asemiconductor device according to a fourth preferred embodiment. TheMOSFET of the fourth preferred embodiment is configured such that apolysilicon layer 10, being a first polysilicon layer covering an innerend portion of a thermal oxide film 9 in a region between an N-typediffusion layer 4 and a P-type diffusion layer 6, has an outer endportion (close to the low-side circuit) that is located closer to alow-side circuit than an outer end portion of an N-type diffusion layer14 formed below the thermal oxide film 9. That is, the polysilicon layer10 extends more outward than the N-type diffusion layer 14.

The N-type diffusion layer 14 has a higher impurity concentration thanan N-type diffusion layer 3 serving as a RESURF region, so that theN-type diffusion layer 14 has a small voltage drop when breakdownvoltage is maintained and high voltage is applied to a drain electrode22 as shown in FIG. 5 , and thus the N-type diffusion layer 14 has ahigher potential than the N-type diffusion layer 3 around it. When thisinfluences a difference in potential between the thermal oxide film 9and the N-type diffusion layer 3 to increase, an electric fieldincreases in an outer end portion of the N-type diffusion layer 14 todeteriorate breakdown voltage performance of the MOSFET. The fourthpreferred embodiment includes the polysilicon layer 10 extending moreoutward than the N-type diffusion layer 14 as illustrated in FIG. 15 ,so that a difference in potential between the N-type diffusion layer 14and the thermal oxide film 9 is reduced. Thus, the fourth preferredembodiment enables increasing the breakdown voltage of the MOSFET.

FIG. 16 shows results of simulating a relationship between a length ofthe polysilicon layer 10 being the first polysilicon layer extendingtoward the low-side circuit and the breakdown voltage of the MOSFET.FIG. 16 has a horizontal axis representing a length of the N-typediffusion layer 14 with reference to an outer end portion of the N-typeburied diffusion layer 2, and a vertical axis. Then, a solid line drawnparallel to the vertical axis represents a position of the outer endportion of the N-type diffusion layer 14. As can be seen from FIG. 16 ,when the polysilicon layer 10 is extended more outward than the N-typediffusion layer 14, the breakdown voltage of the MOSFET is increased.The fourth preferred embodiment may be combined with the second andthird preferred embodiments.

Fifth Preferred Embodiment

FIG. 17 is a sectional view of a MOSFET formed in a RESURF region of asemiconductor device according to a fifth preferred embodiment. Thefirst preferred embodiment (FIG. 1 ) includes the N-type diffusion layer7 serving as the source region of the MOSFET, being formed in the P-typediffusion layer 6 provided in the N-type diffusion layer 3. In contrast,the fifth embodiment includes an N-type diffusion layer 7 formed insidea P-type diffusion layer 1 outside an N-type diffusion layer 3 while aP-type diffusion layer 6 is eliminated, as illustrated in FIG. 17 . FIG.17 illustrates structure in which a gate electrode 21 provided on apolysilicon layer 11 faces a surface of the P-type diffusion layer 1between the N-type diffusion layer 7 and the N-type diffusion layer 3,and a channel is formed in the P-type diffusion layer 1 below the gateelectrode 21 during an ON operation of the MOSFET.

The first preferred embodiment has the structure including the parasiticPNP transistor composed of the P-type diffusion layer 6, the N-typediffusion layer 3, and the P-type diffusion layer 1, and thus a currentflowing through the parasitic PNP transistor (parasitic current) mayincrease power consumption. In contrast, the fifth preferred embodimenthas structure in which such a parasitic PNP transistor is not formed tocause no parasitic current to flow, so that power consumption can bereduced.

The structure of the first preferred embodiment requires the P-typediffusion layer 1 and the P-type diffusion layer 6 to be separated fromeach other. This requires a sufficient distance between the layers to besecured, and thus causes a problem of increase in size of the MOSFET. Incontrast, the structure of the fifth embodiment does not require suchseparation, so that an effect of enabling reduction in size of theMOSFET is achieved. The fifth preferred embodiment may be combined withthe second, third, and fourth preferred embodiments.

Sixth Preferred Embodiment

FIG. 18 is a plan view illustrating a high-side circuit region of aconventional semiconductor device. As illustrated in FIG. 18 , theconventional semiconductor device includes an N-type diffusion layer 202being a second region (RESURF region) that is formed in a P-typesemiconductor substrate 201, and an N-type buried diffusion layer 203being a third region that is formed in an N-type diffusion layer 202.Outside the N-type diffusion layer 202, an electrode 204 to which areference potential (GND potential) of a low-side circuit is supplied isformed, and inside the N-type diffusion layer 202, an electrode 205 towhich a reference potential of a high-side circuit, different from theGND potential, is supplied is formed. When the potential of theelectrode 205 rises, the GND potential and the reference potential ofthe high-side circuit are separated from each other by completelydepleting the N-type diffusion layer 202.

FIG. 19 is a plan view illustrating a high-side circuit region of asemiconductor device of a sixth preferred embodiment. As in FIG. 18 ,the semiconductor device includes an N-type diffusion layer 202 servingas a RESURF region formed in a P-type semiconductor substrate 201, anN-type buried diffusion layer 203 formed in the N-type diffusion layer202, and an electrode 204 formed outside the N-type diffusion layer 202,to which a reference potential (GND potential) of a low-side circuit issupplied. The semiconductor device of the sixth preferred embodimentincludes the N-type diffusion layer 202 serving as a RESURF regionsurrounding the high-side circuit (hatched portion in FIG. 19 ), beingformed with the MOSFET 206 according to the first preferred embodiment.That is, for example, a cross section taken along line a-b shown in FIG.19 shows the structure illustrated in FIG. 1 .

When a layout as illustrated in FIG. 19 is used, the MOSFET can bemounted without additionally providing a region for forming the MOSFET.Additionally, breakdown voltage between the high-side circuit and theGND potential can be increased by the effect described in the firstpreferred embodiment.

The MOSFET formed in the N-type diffusion layer 202 surrounding thehigh-side circuit (hatched portion in FIG. 19 ) may be the MOSFET of thesecond, third, fourth, or fifth embodiment. As illustrated in FIG. 20 ,a MOSFET 206 and another MOSFET 207 electrically separated from theMOSFET 206 may be formed between the high-side circuit and the low-sidecircuit.

Seventh Preferred Embodiment

FIG. 21 is a diagram illustrating a configuration of a drive ICaccording to a seventh preferred embodiment. This drive IC is configuredto drive a switching element that constitutes a half bridge circuit, andincludes a high-side circuit 301 that drives an upper switching element305 a, a low-side circuit 302 that drives a lower switching element 305b, and a level shift circuit 303 that transmits a signal between thehigh-side circuit 301 and the low-side circuit 302. The high-sidecircuit 301 is supplied with driving power from a power supply 304 a,and the low-side circuit 302 is supplied with driving power from thepower supply 304 a. The upper switching element 305 a and the lowerswitching element 305 b each receive a potential from a power supply306.

FIG. 22 is a circuit diagram of the level shift circuit 303. The levelshift circuit 303 includes a resistance element 402, a MOSFET 401, and aresistance element 403, which are connected in series between thehigh-side circuit 301 and a GND potential (reference potential of thelow-side circuit 302). The low-side circuit 302 outputs a signal toswitch on or off the MOSFET 401, and the high-side circuit 301 receivesa voltage signal generated in the resistance element 402. This enablesthe level shift circuit 303 to transmit a signal from the low-sidecircuit 302 to the high-side circuit 301 while separating a referencepotential of the high-side circuit 301 from the reference potential ofthe low-side circuit 302.

The seventh preferred embodiment uses the MOSFET of the first preferredembodiment as the MOSFET 401 of the level shift circuit 303. The MOSFETof the first embodiment has high breakdown voltage performance and lowon-resistance, so that the level shift circuit 303 can be operated in awider range of potentials and power consumption can be reduced. As theMOSFET 401 of the level shift circuit 303, the MOSFET of the second,third, fourth, or fifth embodiment may be used. The high-side circuit301, the low-side circuit 302, and the level shift circuit 303 may beformed in the same chip, or may be separated into separate respectivechips.

In FIG. 21 , a bootstrap circuit may be used instead of the power supply304 a of the high-side circuit 301. FIG. 23 illustrates an example inwhich a bootstrap circuit is used as the power supply of the high-sidecircuit 301.

The bootstrap circuit includes a limiting resistor 307, a bootstrapdiode 308, and a bootstrap capacitor 309. The limiting resistor 307 andthe bootstrap diode 308 are connected in series between the power supply304 b of the low-side circuit 302 and a power input terminal of thehigh-side circuit 301. The bootstrap capacitor 309 is connected betweena connection node between the upper switching element 305 a and thelower switching element 305 b, and the power input terminal of thehigh-side circuit 301.

A Vs potential at the connection node between the upper switchingelement 305 a and the lower switching element 305 b changes between apotential of the power supply 306 and the GND potential when the upperswitching element 305 a and the lower switching element 305 b are turnedon and off. When the Vs potential equals the GND potential, a chargefrom the power supply 304 b is supplied to the bootstrap capacitor 309through the bootstrap diode 308 to charge the bootstrap capacitor 309.After that, when the Vs potential changes to the potential of the powersupply 306, a charge is supplied from the bootstrap capacitor 309 to thepower input terminal of the high-side circuit 301, and thus thebootstrap capacitor 309 functions as a power supply of the high-sidecircuit 301. At this time, the bootstrap diode 308 functions to preventa current from flowing into the power supply 304 b. The limitingresistor 307 functions to limit a current for charging the bootstrapcapacitor 309 to a desired value.

Eighth Preferred Embodiment

FIG. 24 is a configuration diagram of a drive IC according to an eighthpreferred embodiment. The drive IC of the eighth preferred embodiment isconfigured such that the limiting resistor 307 and bootstrap diode 308of FIG. 23 are replaced with the MOSFET 310 of the first preferredembodiment and the MOSFET 310 is used as a bootstrap diode.

The MOSFET 310 is formed in a RESURF region that separates a high-sidecircuit 301 and a low-side circuit 302 from each other, as in the fifthpreferred embodiment. This enables forming a bootstrap circuit thatfunctions as a power supply for the high-side circuit 301 without usinga high breakdown voltage element different from the drive IC includingthe high-side circuit 301 and the low-side circuit 302. As a result,this can contribute to miniaturization of a driving device including thedrive IC of the half bridge circuit. The MOSFET 310 in FIG. 24 may bethe MOSFET of the second, third, fourth, or fifth preferred embodiment.The high-side circuit 301, the low-side circuit 302, and the level shiftcircuit 303 may be formed in the same chip, or may be separated intoseparate respective chips.

Ninth Preferred Embodiment

FIG. 25 is a sectional view of a MOSFET formed in a RESURF region of asemiconductor device according to a ninth preferred embodiment. FIG. 25illustrates structure that is different from the structure of FIG. 1 inthat an N-type diffusion layer 16 having a higher peak concentration ofimpurities than the N-type diffusion layer 3 is formed as a thirdregion, instead of the N-type buried diffusion layer 2. Although theN-type buried diffusion layer 2 is buried inside a semiconductorsubstrate 100 (near a bottom portion of the N-type diffusion layer 3),the N-type diffusion layer 16 is formed from a surface portion of thesemiconductor substrate 100 to the bottom portion of the N-typediffusion layer 3. The N-type diffusion layer 16 is deeper than theN-type diffusion layer 14.

Additionally, the N-type diffusion layer 16 does not satisfy the RESURFcondition. That is, when the N-type diffusion layer 16 has an impurityconcentration indicated as N [cm⁻³] and a depth indicated as t [cm], arelationship, N×t>6.9×10¹¹ cm⁻², is satisfied. Thus, the ninth preferredembodiment does not allow the N-type diffusion layer 16 to be completelydepleted when breakdown voltage is maintained, and allows an electricfield to be concentrated in an outer end portion of the N-type diffusionlayer 16. This causes the electric field to concentrate in both theN-type diffusion layer 14 and the N-type diffusion layer 16, so that anoperation and an effect as in the first preferred embodiment can beobtained. Even in the present embodiment, the N-type diffusion layer 5may be eliminated.

The ninth preferred embodiment does not require a diffusion layer havingstructure embedded inside the semiconductor substrate 100 to be formed.This enables a semiconductor device having an operation and an effect asin the first preferred embodiment to be formed by a usual impuritydiffusion step. The ninth embodiment may be also applied to thesemiconductor device of the second, third, fourth, fifth, sixth,seventh, or eighth embodiment to replace the N-type buried diffusionlayer 2 with the N-type diffusion layer 16.

The respective embodiments can be freely combined, or the respectiveembodiments can be appropriately modified or eliminated.

While the disclosure has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of thedisclosure.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate formed with a first region of a firstconductivity type; a second region that is a RESURF region of a secondconductivity type formed in a surface portion of the first region toseparate a high-side circuit and a low-side circuit from each other; athird region of the second conductivity type formed at least in a bottomportion of the second region close to the high-side circuit, having ahigher peak concentration of impurities than the second region; and aMOSFET using the second region as a drift layer, the MOSFET including: afourth region serving as a drain region of the second conductivity typeformed in the surface portion of the second region, having a higher peakconcentration of impurities than the second region; a sixth regionserving as a source region of the second conductivity type formed in asurface portion of a fifth region of the first conductivity type or in asurface portion of the first region, in a region closer to the low-sidecircuit than the fourth region, the fifth region being provided in thesecond region; a first thermal oxide film formed on a surface of thesecond region, in a region between the fourth region and the sixthregion; and a seventh region of the second conductivity type formed in asurface portion of the second region below the first thermal oxide film,having a higher peak concentration of impurities than the second region,wherein an end portion of the seventh region close to the low-sidecircuit is located closer to the low-side circuit than an end portion ofthe third region close to the low-side circuit, the third region reachesa surface of the second region, and when the third region has animpurity concentration indicated as N [cm⁻³] and a depth indicated as t[cm], the relationship, N×t>6.9×10¹¹ cm⁻², is satisfied.
 2. Asemiconductor device comprising: a semiconductor substrate formed with afirst region of a first conductivity type; a second region that is aRESURF region of a second conductivity type formed in a surface portionof the first region to separate a high-side circuit and a low-sidecircuit from each other; a third region of the second conductivity typeformed at least in a bottom portion of the second region close to thehigh-side circuit, having a higher peak concentration of impurities thanthe second region; and a MOSFET using the second region as a driftlayer, the MOSFET including: a fourth region serving as a drain regionof the second conductivity type formed in the surface portion of thesecond region, having a higher peak concentration of impurities than thesecond region; a sixth region serving as a source region of the secondconductivity type formed in a surface portion of a fifth region of thefirst conductivity type or in a surface portion of the first region, ina region closer to the low-side circuit than the fourth region, thefifth region being provided in the second region; a first thermal oxidefilm formed on a surface of the second region, in a region between thefourth region and the sixth region; and a seventh region of the secondconductivity type formed in a surface portion of the second region belowthe first thermal oxide film, having a higher peak concentration ofimpurities than the second region, wherein an end portion of the seventhregion close to the low-side circuit is located closer to the low-sidecircuit than an end portion of the third region close to the low-sidecircuit, the semiconductor device further comprising: a second thermaloxide film formed on the surface of the second region, closer to thehigh-side circuit than the fourth region; and an eighth region of thesecond conductivity type formed below the second thermal oxide film,having a higher peak concentration of impurities than the second region,and when the eighth region has an impurity concentration indicated as N1and the seventh region has an impurity concentration indicated as N2, arelationship, 0.1×N1<N2<2×N1, is satisfied.
 3. A semiconductor devicecomprising: a semiconductor substrate formed with a first region of afirst conductivity type; a second region that is a RESURF region of asecond conductivity type formed in a surface portion of the first regionto separate a high-side circuit and a low-side circuit from each other;a third region of the second conductivity type formed at least in abottom portion of the second region close to the high-side circuit,having a higher peak concentration of impurities than the second region;and a MOSFET using the second region as a drift layer, the MOSFETincluding: a fourth region serving as a drain region of the secondconductivity type formed in the surface portion of the second region,having a higher peak concentration of impurities than the second region;a sixth region serving as a source region of the second conductivitytype formed in a surface portion of a fifth region of the firstconductivity type or in a surface portion of the first region, in aregion closer to the low-side circuit than the fourth region, the fifthregion being provided in the second region; a first thermal oxide filmformed on a surface of the second region, in a region between the fourthregion and the sixth region; and a seventh region of the secondconductivity type formed in a surface portion of the second region belowthe first thermal oxide film, having a higher peak concentration ofimpurities than the second region, wherein an end portion of the seventhregion close to the low-side circuit is located closer to the low-sidecircuit than an end portion of the third region close to the low-sidecircuit, and the semiconductor device further comprising: a ninth regionof the second conductivity type formed in a region closer to thelow-side circuit than the seventh region, having a peak concentration ofimpurities lower than the seventh region and higher than the secondregion.
 4. A semiconductor device comprising: a semiconductor substrateformed with a first region of a first conductivity type; a second regionthat is a RESURF region of a second conductivity type formed in asurface portion of the first region to separate a high-side circuit anda low-side circuit from each other; a third region of the secondconductivity type formed at least in a bottom portion of the secondregion close to the high-side circuit, having a higher peakconcentration of impurities than the second region; and a MOSFET usingthe second region as a drift layer, the MOSFET including: a fourthregion serving as a drain region of the second conductivity type formedin the surface portion of the second region, having a higher peakconcentration of impurities than the second region; a sixth regionserving as a source region of the second conductivity type formed in asurface portion of a fifth region of the first conductivity type or in asurface portion of the first region, in a region closer to the low-sidecircuit than the fourth region, the fifth region being provided in thesecond region; a first thermal oxide film formed on a surface of thesecond region, in a region between the fourth region and the sixthregion; and a seventh region of the second conductivity type formed in asurface portion of the second region below the first thermal oxide film,having a higher peak concentration of impurities than the second region,wherein an end portion of the seventh region close to the low-sidecircuit is located closer to the low-side circuit than an end portion ofthe third region close to the low-side circuit, and the semiconductordevice further comprising: a ninth region of the second conductivitytype formed discretely in a region closer to the low-side circuit thanthe seventh region, having a peak concentration of impurities equal toor lower than the seventh region and higher than the second region.
 5. Asemiconductor device comprising: a semiconductor substrate formed with afirst region of a first conductivity type; a second region that is aRESURF region of a second conductivity type formed in a surface portionof the first region to separate a high-side circuit and a low-sidecircuit from each other; a third region of the second conductivity typeformed at least in a bottom portion of the second region close to thehigh-side circuit, having a higher peak concentration of impurities thanthe second region; and a MOSFET using the second region as a driftlayer, the MOSFET including: a fourth region serving as a drain regionof the second conductivity type formed in the surface portion of thesecond region, having a higher peak concentration of impurities than thesecond region; a sixth region serving as a source region of the secondconductivity type formed in a surface portion of a fifth region of thefirst conductivity type or in a surface portion of the first region, ina region closer to the low-side circuit than the fourth region, thefifth region being provided in the second region; a first thermal oxidefilm formed on a surface of the second region, in a region between thefourth region and the sixth region; and a seventh region of the secondconductivity type formed in a surface portion of the second region belowthe first thermal oxide film, having a higher peak concentration ofimpurities than the second region, wherein an end portion of the seventhregion close to the low-side circuit is located closer to the low-sidecircuit than an end portion of the third region close to the low-sidecircuit, and the seventh region includes a portion close to the low-sidecircuit, having an impurity concentration higher than a portion close tothe high-side circuit.
 6. A semiconductor device comprising: asemiconductor substrate formed with a first region of a firstconductivity type; a second region that is a RESURF region of a secondconductivity type formed in a surface portion of the first region toseparate a high-side circuit and a low-side circuit from each other; athird region of the second conductivity type formed at least in a bottomportion of the second region close to the high-side circuit, having ahigher peak concentration of impurities than the second region; and aMOSFET using the second region as a drift layer, the MOSFET including: afourth region serving as a drain region of the second conductivity typeformed in the surface portion of the second region, having a higher peakconcentration of impurities than the second region; a sixth regionserving as a source region of the second conductivity type formed in asurface portion of a fifth region of the first conductivity type or in asurface portion of the first region, in a region closer to the low-sidecircuit than the fourth region, the fifth region being provided in thesecond region; a first thermal oxide film formed on a surface of thesecond region, in a region between the fourth region and the sixthregion; and a seventh region of the second conductivity type formed in asurface portion of the second region below the first thermal oxide film,having a higher peak concentration of impurities than the second region,wherein an end portion of the seventh region close to the low-sidecircuit is located closer to the low-side circuit than an end portion ofthe third region close to the low-side circuit, the semiconductor devicefurther comprising: a polysilicon layer formed on an end portion of thefirst thermal oxide film close to the high-side circuit, and an endportion of the polysilicon layer close to the low-side circuit islocated closer to the low-side circuit than an end portion of theseventh region close to the low-side circuit.
 7. The semiconductordevice according to claim 1, wherein the MOSFET functions as a bootstrapdiode that supplies power to the high-side circuit.
 8. The semiconductordevice according to claim 2, wherein the MOSFET functions as a bootstrapdiode that supplies power to the high-side circuit.
 9. The semiconductordevice according to claim 3, wherein the MOSFET functions as a bootstrapdiode that supplies power to the high-side circuit.
 10. Thesemiconductor device according to claim 4, wherein the MOSFET functionsas a bootstrap diode that supplies power to the high-side circuit. 11.The semiconductor device according to claim 5, wherein the MOSFETfunctions as a bootstrap diode that supplies power to the high-sidecircuit.
 12. The semiconductor device according to claim 6, wherein theMOSFET functions as a bootstrap diode that supplies power to thehigh-side circuit.
 13. An integrated circuit comprising thesemiconductor device according to claim
 1. 14. An integrated circuitcomprising the semiconductor device according to claim
 2. 15. Anintegrated circuit comprising the semiconductor device according toclaim
 3. 16. An integrated circuit comprising the semiconductor deviceaccording to claim
 4. 17. An integrated circuit comprising thesemiconductor device according to claim
 5. 18. An integrated circuitcomprising the semiconductor device according to claim 6.